Adding a dummy register read before changing the D/C signal fixed the issue I was having earlier. That proves that logic analysers shorten troubleshooting time dramatically: I’d have been blind without one 🙂
The STM32F100’s SPI status register seems to behave oddly as sometimes the busy flag is clear before a full byte is transferred over the bus. I should probably try to use DMA next, to see if it behaves well, as my fix is SPI frequency dependant (however, I am running at max frequency for this SPI port I use, 12 MHz, so it should be fine for all other prescaler values).
The good thing about this MCU is that I can switch SPI to 16 bit data during screen filling and bitmap copying, which is slightly faster than sending MSB and then LSB separately 🙂
 If it wasn’t for the fact that the busy flag sometimes is cleared after a byte has been fully transmitted on the SPI bus, I’d be inclined to say that the busy flag is only indicating whether the SPI data register is ready to be written to again, rather than whether the last byte written to it has been transferred on the SPI bus. I can think of a good reason for ST to implement the flag in such a way: by the time an application finishes writing to the SPI data register again, the previous byte has nearly been transferred on the SPI bus, so the throughput on the SPI bus is maximum 🙂